SID-6581D   Project

(V-SID 1.0/2.0)

 

>>New: some MP3s of the VSID 2.0 are now available. See below <<

 

 

The SID-6581D project (or V-SID 1.0) has begun in March 2005, by David Amoros.

After he discovered the Bob Yannes’s interview (the creator of the SID chip) on internet, he decided to create an emulation of the SID behaviour in a FPGA (EP1C12 Cyclone Altera).

The FPGA contains the VSID 1.0 engine and a 32-bit CPU to converts the commands received from the RS-232 interface into data sent to the engine.

The following figure shows a functional description of the project:

 

The main features of the VSID 1.0 engine are the following:

·       Sampling frequency: 1 MHz

·       Three oscillators with: tri, saw, pulse, noise waveforms, in 12-bit resolution, ring modulation, hard-sync, waveform mixing

·       Three 8-bit amplitude modulators, with 3 ADSR envelope generators (exponential decay and release)

·       One mixer

·       One IIR filter with 16-bit coefficients controlled by CPU (resonant low-pass filter only)

·       2nd order delta-sigma DAC

 

The main tasks of the 32-bit CPU software are the following:

·       Display and switches processing

·       MIDI commands processing

·       software LFO (tri/square/saw waveforms)

·       filter coefficients stored in the program memory (128 cut-off frequencies x 16 resonance levels x 5 coefficients = 10240 16-bit values)

 

All the parameters of the VSID 1.0 are programmable with the switches and the display. Moreover, each oscillator has its own MIDI channel to allow playing 3-track songs.

 

 

Picture 1: Development board power-on

 

 

When the development board is powered-on, the display prints -PLAY- in order to indicate that everything is OK.

 

Picture 2: Detune parameter

 

Picture 3: Filter cut-off frequency parameter

 

Picture 4: LFO type parameter

 

 

Parameter description

In edit mode, the display prints the following information:

·       The first digit (on the left) displays the voice (1, 2 or 3) or the filter/output (F) or the LFO (L) parameter category

·       The two following digits display the parameter that depends on the selected category

Ø    Dt: detune for the selected voice

Ø    Pl : pulse width for the selected voice

Ø    Tr: triangle waveform switch for the selected voice

Ø    Ps: pulse waveform switch for the selected voice

Ø    Sa: saw waveform switch for the selected voice

Ø    Ns: noise waveform switch for the selected voice

Ø    Rs: ring mod switch for the selected voice

Ø    Ss: hard-sync switch for the selected voice

Ø    At: envelope attack rate for the selected voice

Ø    Dc: envelope decay rate for the selected voice

Ø    Su: envelope sustain level for the selected voice

Ø    Rl: envelope release rate for the selected voice

Ø    Ch: MIDI channel for the selected voice

Ø    Fr: cut-off frequency for the filter

Ø    Re: resonance for the filter

Ø    Le: level for the output

Ø    Ty: waveform for the LFO

Ø    Ra: rate for the LFO

Ø    F1: modulation depth applied to the frequency of voice 1 (LFO)

Ø    F2: modulation depth applied to the frequency of voice 2 (LFO)

Ø    F3: modulation depth applied to the frequency of voice 3 (LFO)

Ø    P1: modulation depth applied to the pulse width of voice 1 (LFO)

Ø    P2: modulation depth applied to the pulse width of voice 2 (LFO)

Ø    P3: modulation depth applied to the pulse width of voice 3 (LFO)

·       The three last digits display the parameter value.

 

The 32-bit CPU processes the following MIDI messages:

·       Note ON/OFF

·       Modulation wheel for the pulse width modulation

·       CC-74 for the cut-off frequency of the filter

·       CC-71 for the resonance of the filter

 

Picture 5: Overview

 

VSID 1.0 development

Here is the heart of the VSID 1.0 engine:

 

 

Here is an extract of the fitting report (including the 32-bit CPU, the switches and display interfaces):

 

+------------------------------------------------------------+

; Fitter Resource Usage Summary                              ;

+--------------------------------+---------------------------+

; Resource                       ; Usage                     ;

+--------------------------------+---------------------------+

; Logic cells                    ; 8,755 / 12,060 ( 72 % )   ;

; Registers                      ; 3,016 / 12,795 ( 23 % )   ;

; Total LABs                     ; 1,029 / 1,206 ( 85 % )    ;

; Logic elements in carry chains ; 2062                      ;

; User inserted logic cells      ; 0                         ;

; Virtual pins                   ; 0                         ;

; I/O pins                       ; 99 / 249 ( 39 % )         ;

;     -- Clock pins              ; 0 / 2 ( 0 % )             ;

; Global signals                 ; 5                         ;

; M4Ks                           ; 13 / 52 ( 25 % )          ;

; Total memory bits              ; 51,072 / 239,616 ( 21 % ) ;

; Total RAM block bits           ; 59,904 / 239,616 ( 25 % ) ;

; Global clocks                  ; 5 / 8 ( 62 % )            ;

; Maximum fan-out node           ; rstn                      ;

; Maximum fan-out                ; 1843                      ;

; Total fan-out                  ; 37096                     ;

; Average fan-out                ; 4.18                      ;

+--------------------------------+---------------------------+

 

The VSID 1.0 engine takes a little bit more than 6,000 logic cells.

 

 

Audio demo (MP3)

It’s time now to listen to the result of the emulation (click on the links below):

 

demo 1: 3-voice demo, with real-time filter sweeps.

demo 2: Entertain demo from the SIDSTATION (http://www.elektron.se) recreated and played by the VSID 1.0 engine. The LFO is applied to the pulse width.

demo 3: Bass sound with PWM and filter sweeps.

 

 

Next step…

As you can imagine, the VSID 2.0 engine is in development, and will be a great improvement compared to the VSID 1.0 engine. Here are some new features:

·       Emulation of the 6581 or 8580 chips

·       Analogue modelling of the SID filter (low-pass, band-pass, high-pass, with 2048 cut-off frequency values)

·       Selectable bit reduction for oscillator and envelope outputs for LO-FI effects

·       Envelopes can be disconnected from the amplitude modulators and be connected directly to the filter cut-off frequency, pulse width, waveform selection.

·       Oscillators can be used as modulators for phase, pulse width, filter cut-off frequency, waveform, amplitude

·       2nd  order delta-sigma DAC (in the FPGA but external from the VSID engine), (a 3rd-order version will be used at the end of the project)

·       Each parameter will be controlled by MIDI

·       Hardware matrix modulation

·       Etc…

 

News: VSID 2.0 engine development status

March 25th 2007

ü    The VSID 2.0 engine is designed at 100 %.

 

Here is the heart of the VSID 2.0:

Note: You can notice the complexity of the VSID 2.0 compared to the VSID 1.0.

 

Ø    Integration and connection to the CPU is on-going.

 

April 1st 2007

ü    Integration and connection between the different components of the project is completed:

 

Note: for that moment, the delta-sigma DAC is always a 2nd order one.

 

Here is the fitting report including:

+-------------------------------------------------------------+

; Fitter Resource Usage Summary                               ;

+--------------------------------+----------------------------+

; Resource                       ; Usage                      ;

+--------------------------------+----------------------------+

; Logic cells                    ; 6,154 / 12,060 ( 51 % )    ;

; Registers                      ; 2,354 / 12,795 ( 18 % )    ;

; Total LABs                     ; 779 / 1,206 ( 64 % )       ;

; Logic elements in carry chains ; 1231                       ;

; User inserted logic cells      ; 0                          ;

; Virtual pins                   ; 0                          ;

; I/O pins                       ; 45 / 249 ( 18 % )          ;

;     -- Clock pins              ; 0 / 2 ( 0 % )              ;

; Global signals                 ; 4                          ;

; M4Ks                           ; 43 / 52 ( 82 % )           ;

; Total memory bits              ; 112,512 / 239,616 ( 46 % ) ;

; Total RAM block bits           ; 198,144 / 239,616 ( 82 % ) ;

; Global clocks                  ; 4 / 8 ( 50 % )             ;

; Maximum fan-out node           ; rstn                       ;

; Maximum fan-out                ; 1428                       ;

; Total fan-out                  ; 28426                      ;

; Average fan-out                ; 4.55                       ;

+--------------------------------+----------------------------+

Note 1: The VSID 2.0 engine uses less resource than the VSID 1.0 engine thanks to the usage of wired micro-instructions for the digital filter.

It explains why the VSID 2.0 engine uses an 8-MHz functional clock (1-MHz functional clock for the VSID 1.0 engine).

 

Note 2: The VSID 1.0 is configured from the switches/display on the development board, whereas all the parameters of the VSID 2.0 will be only accessible via the MIDI protocol through the RS-232 port. Since the switches and display interfaces are not implemented, some resources are saved in the FPGA!

 

Ø    The development of the NIOS CPU software is on-going. The software will process the MIDI commands received from the RS-232 port; it will also generate a software pitch envelope and six modulation tables; it will finally control the VSID 2.0 engine.

 

April 15th 2007

To test the NIOS CPU software and to control the VSID 2.0 engine, a MIDI editor is necessary. I have developed such an editor with SynthEdit:

 

Each switch, slider, and list sends a MIDI control change message. You can see the editor windows for the three oscillators (with the new parameter “Bit reduction”), the editor windows for the three envelope generators (with the new parameter “Bit reduction”, and the capability of replacing the sustain level by the note-on velocity value), the editor window for the filter/output (analogue modelling version of the original SID filter, with selection of the output stage saturation type and the emulated chip type 6581 or 8580).

The last editor window (VSID modulations) allows setting the modulation sources for 14 destinations (pitch, pulse width, level and waveform destinations for each oscillator, filter cut-off frequency destination and output volume destination), setting the one-segment pitch envelope, setting the master tempo for all modulation tables, setting the table parameters and the table steps for each table (6 modulation tables).

 

Special thanks to:

·       Jeff McClintock for SynthEdit software (http://www.synthedit.com)

·       David Haupt for its MIDI library for SynthEdit (http://www.dehaupt.com/SynthEdit)

 

Next Rendezvous: end of May for preliminary tests with the VSID2.0 engine.

 

May 27th 2007

Ø    Here are the first MP3 samples of the VSID 2.0 engine:

 

SID 6581 bells: ring-modulated sound played at different octaves.

FM: this example demonstrates the frequency modulation between 2 oscillators. The modulation depth is controlled by the modulation wheel.

Snare drum: snare drum sound played at different octaves. Two oscillators are used: one with triangle waveform, the other with noise waveform.

Square bass: square bass sound with resonant low-pass filter. The cut-off frequency is controlled by the modulation wheel.

Filtered saw waves 1: detuned saw waves filtered by the high-pass filter controlled by an envelope.

Filtered saw waves 2: detuned saw waves filtered by the band-pass filter controlled by an envelope.

Wave sequence: wave sequence controlled by an envelope.

Digital saturation: 3 oscillators filtered by the low-pass filter with digital saturation.

 

Remaining tasks to do:

6 modulation tables and a pitch envelope must be implemented.

Rendezvous by end of June for new MP3s

 

Contact:

You can contact me by e-mail for more information: amoros-david@wanadoo.fr